// Copyright (C) 1953-2022 NUDT
// Verilog module name - tsn_packet_lookup
// Version: V4.0.0.20220524
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         packet maps.
///////////////////////////////////////////////////////////////////////////


module tsn_packet_lookup
(
        i_clk              ,   
        i_rst_n            ,
        
        i_cyclestart      ,
        iv_inject_period   ,
        
        iv_md              ,
		i_md_wr            ,	
        
        iv_flowidram_addr  ,
        iv_flowidram_wdata ,
        i_flowidram_wr     ,
        ov_flowidram_rdata ,
        i_flowidram_rd     ,
        
        ov_md              , 
        o_md_wr            
         
);
// I/O
// clk & rst  
input               i_clk  ;
input               i_rst_n;

input               i_cyclestart;
input      [10:0]   iv_inject_period;
//5tuple & dmac input
input      [299:0]  iv_md  ;
input               i_md_wr;

input      [13:0]   iv_flowidram_addr     ;
input      [73:0]   iv_flowidram_wdata    ;
input               i_flowidram_wr        ;
output     [73:0]   ov_flowidram_rdata    ;
input               i_flowidram_rd        ;
//tsntag & bufid output 
output     [299:0]  ov_md  ;
output              o_md_wr;
//***************************************************
//          extract five tuple from pkt 
//***************************************************
// internal reg&wire for state machine
wire   [13:0]       wv_ram_raddr_b_tlu2ram;
wire                w_ram_rd_b_tlu2ram    ;
wire   [73:0]       wv_ram_rdata_b_ram2tlu;

wire                w_ram_wr_b_ram2tlu     ;
wire   [13:0]       wv_ram_waddr_b_ram2tlu ;
wire   [73:0]       wv_ram_wdata_b_ram2tlu ;

wire   [13:0]       wv_ram_addr_b_ram2tlu  ;

wire   [299:0]      wv_md_flt2tpa    ;
wire                w_md_wr_flt2tpa  ;

assign wv_ram_addr_b_ram2tlu = w_ram_rd_b_tlu2ram ? wv_ram_raddr_b_tlu2ram : wv_ram_waddr_b_ram2tlu;
flowid_lookup flowid_lookup_inst(                           
.i_clk                          (i_clk),
.i_rst_n                        (i_rst_n),
                               
.iv_md                          (iv_md),
.i_md_wr                        (i_md_wr),
                               
.ov_ram_raddr                   (wv_ram_raddr_b_tlu2ram),
.o_ram_rd                       (w_ram_rd_b_tlu2ram),
                               
.ov_md                          (wv_md_flt2tpa  ),
.o_md_wr                        (w_md_wr_flt2tpa)
);

tsn_packet_action tsn_packet_action_inst(
.i_clk                          (i_clk),
.i_rst_n                        (i_rst_n),

.i_cyclestart                  (i_cyclestart),
.iv_inject_period               (iv_inject_period),
                              
.iv_md                          (wv_md_flt2tpa),
.i_md_wr                        (w_md_wr_flt2tpa),
                                                               
.iv_ram_rdata                   (wv_ram_rdata_b_ram2tlu              ),
.o_ram_wr                       (w_ram_wr_b_ram2tlu    ),  
.ov_ram_waddr                   (wv_ram_waddr_b_ram2tlu),
.ov_ram_wdata                   (wv_ram_wdata_b_ram2tlu),
                              
.ov_md                          (ov_md  ),
.o_md_wr                        (o_md_wr)
);
//`ifdef altera_ip
tdpr_singleclock_rdenab_outputaclrab_w74d16384 truedualportram_singleclock_rdenab_outputaclrab_w74d16384_inst(
.aclr                          (!i_rst_n),
                              
.address_a                     (iv_flowidram_addr),
.address_b                     (wv_ram_addr_b_ram2tlu),
                             
.clock                         (i_clk),
                             
.data_a                        (iv_flowidram_wdata),
.data_b                        (wv_ram_wdata_b_ram2tlu),
                              
.rden_a                        (i_flowidram_rd),
.rden_b                        (w_ram_rd_b_tlu2ram),
                             
.wren_a                        (i_flowidram_wr),
.wren_b                        (w_ram_wr_b_ram2tlu),
                              
.q_a                           (ov_flowidram_rdata),
.q_b                           (wv_ram_rdata_b_ram2tlu)
);
//`endif
`ifdef xilinx_ip
truedualportram_singleclock_rdenab_outputaclrab_w74d16384 truedualportram_singleclock_rdenab_outputaclrab_w74d16384_inst(
.rsta                      (!i_rst_n),
.rstb                      (!i_rst_n),
     
.regcea                    (1'b1),
.regceb                    (1'b1),
                              
.addra                     (iv_flowidram_addr),
.addrb                     (wv_ram_addr_b_ram2tlu),
                             
.clka                      (i_clk),
.clkb                      (i_clk),
                             
.dina                       (iv_flowidram_wdata),
.dinb                       (wv_ram_wdata_b_ram2tlu),
                              
.ena                        (1'b1),
.enb                        (1'b1),
                             
.wea                        (i_flowidram_wr),
.web                        (w_ram_wr_b_ram2tlu),
                              
.douta                      (ov_flowidram_rdata),
.doutb                      (wv_ram_rdata_b_ram2tlu)
);
`endif
endmodule           

